Japanese Patent Application No. 2000-206588, filed Jul. 7, 2000, is hereby incorporated by reference in its entirety.
The present invention relates to a ferroelectric memory device. More particularly, the present invention relates to a simple matrix ferroelectric memory device using only ferroelectric capacitors in which no cell transistor is used, and a method of manufacturing the same.
In semiconductor memories, a memory cell array and peripheral circuits for selectively allowing information to be written into or read from memory cells are generally formed on a single substrate. Therefore, the memory cell array and the peripheral circuits are arranged in the same plane. This results in an increase in the chip area, whereby the degree of integration of the memory cells is limited.
An objective of the present invention is to provide a ferroelectric memory device capable of significantly increasing the degree of integration of memory cells and decreasing the chip area, and a method of manufacturing the same.
A ferroelectric memory device according to the present invention comprises:
a memory cell array, in which memory cells are arranged in a matrix, including first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes; and
a peripheral circuit section for selectively performing information write or information read with respect to the memory cells,
wherein the memory cell array and the peripheral circuit section are disposed in different layers.
According to this ferroelectric memory device, the layout area can be significantly decreased in comparison with the case of disposing the peripheral circuit section and the memory cell array on a single plane, by disposing the memory cell array and the peripheral circuit section in different layers in a layered manner, for example. Therefore, the size of the device can be decreased and the degree of integration of the memory cells can be significantly increased.
In this ferroelectric memory device, the first signal electrodes are electrodes for selecting either rows or columns. The second signal electrodes are electrodes for selecting columns when the first signal electrodes select rows. The second signal electrodes are electrodes for selecting rows when the first signal electrodes select columns.
As configurations in which the memory cell array and the peripheral circuit section are disposed in different layers, the following configurations can be given. Specific effects of these configurations are described later.
(1) The memory cell array and the peripheral circuit section may be layered on a single semiconductor substrate in order from the peripheral circuit section to the memory cell array. Specifically, the peripheral circuit section including an electronic device such as a MOS transistor may be formed on a semiconductor substrate, and the memory cell array may be formed on the peripheral circuit section.
(2) The memory cell array and the peripheral circuit section may be formed in different chips, to form a memory cell array chip and a peripheral circuit chip, respectively. The memory cell array chip and the peripheral circuit chip may be layered on a mounting base in the order from the peripheral circuit chip to the memory cell array chip or in the order from the memory cell array chip to the peripheral circuit chip.
In the case of this embodiment, the mounting base may have a depressed portion for a chip to be positioned, and the peripheral circuit chip and the memory cell array chip may be mounted in the depressed portion in a layered manner. Moreover, a semiconductor, glass, or plastic may be used as a material for the mounting base by forming the peripheral circuit section and the memory cell array in the chips, whereby selectivity of the material for the mounting base can be increased.
The memory cell array may have various configurations. Some of these configurations are illustrated below. Actions and effects of these configurations are described later.
(1) The memory cell array may comprise an underlying layer formed of a ferroelectric material or a material having a crystal structure similar to a structure of a ferroelectric, on a substrate, and the first signal electrodes, the ferroelectric layer, and the second signal electrodes may be layered on the underlying layer.
(2) The memory cell array may comprise an insulating substrate, the first signal electrodes provided in grooves formed in the insulating substrate, the ferroelectric layer, and the second signal electrodes, and the ferroelectric layer and the second signal electrodes may be layered on the insulating substrate on which the first signal electrodes are formed. The insulating substrate used herein refers to a substrate of which at least the surface area on which the first signal electrodes are formed has insulating properties. The insulating substrate may be a substrate formed of a conductive material of which only the surface area has insulating properties.
(3) The memory cell array may comprise an insulating substrate on which is formed depressed portions and projected portions in a given pattern, the first signal electrodes, may be formed at a bottom of the depressed portions and an upper side of the projected portions, and the ferroelectric layer and the second signal electrodes may be layered on the insulating substrate on which the first signal electrodes are formed.
(4) the memory cell array may comprise an insulating substrate on which is formed the first signal electrodes, the ferroelectric layers, and the second signal electrodes, the ferroelectric layer may be formed in a divided manner and disposed in the intersection regions between the first signal electrodes and the second signal electrodes, and dielectric layers differing from the ferroelectric layers may be formed between the adjacent divided ferroelectric layers. The dielectric layers may be formed of a material with a dielectric constant smaller than a dielectric constant of the ferroelectric layer.
In the ferroelectric memory device according to the present invention, a plurality of unit blocks of memory devices may be arranged in a given pattern. Examples of this aspect are described below.
(1) A ferroelectric memory device including an array of ferroelectric memory devices, comprising a plurality of unit blocks of the above-described ferroelectric memory devices arranged in a given pattern.
Such a ferroelectric memory device may comprise:
a plurality of depressed portions having a given shape disposed in a mounting base in a given pattern, and
a memory cell array and a peripheral circuit section which are formed in different chips to form a memory cell array chip and a peripheral circuit chip, respectively, and
the memory cell array chip and the peripheral circuit chip may have a given shape corresponding to a shape of each of the depressed portions in a layered manner, and
the peripheral circuit chip and the memory cell array chip may be layered in each of the depressed portions. In this case, the order of layering the peripheral circuit section chip and the memory cell array chip is not limited. The memory cell array chip may be layered on the peripheral circuit chip, or the peripheral circuit chip may be layered on the memory cell array chip.
(2) A ferroelectric memory device comprising a plurality of unit blocks of at least memory cell arrays arranged in a given pattern. In this case, at least part of a peripheral circuit section may be disposed between the unit blocks.
The ferroelectric memory device according to the present invention may comprise a plurality of sets of a memory cell array and a peripheral circuit section layered on an insulating substrate. In this case, the memory cell array and the peripheral circuit section may be formed in different chips, to form a memory cell array chip and a peripheral circuit chip, respectively.
The ferroelectric memory device according to the present invention may be obtained by a method of manufacturing a ferroelectric memory device comprising the following steps (a) and (b).
(a) a step of forming a peripheral circuit section for selectively writing or reading information into or from memory cells on a semiconductor substrate; and
(b) a step of forming at least first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes on the peripheral circuit section, so as to form a memory cell array in which memory cells are arranged in a matrix.
The ferroelectric memory device according to the present invention may be obtained by a method of manufacturing a ferroelectric memory device in which a peripheral circuit chip and a memory cell array chip are mounted in a layered manner using FSA (Fluidic Self-Assembly), the method comprising the following steps (a) to (d).
(a) a step of forming one or more depressed portions having a given pattern in a mounting base,
(b) a step of forming the peripheral circuit chip and the memory cell array chip having a given shape corresponding to a shape of each of the depressed portions,
(c) a step of supplying liquid, in which the peripheral circuit chip or the memory cell array chip is included, on the surface of the mounting base, to position the peripheral circuit chip or the memory cell array chip in the one or more depressed portions, and
(d) a step of supplying liquid, in which the memory cell array chip or the peripheral circuit chip is included, on the surface of the mounting base, to position the peripheral circuit chip or the memory cell array chip, which is a different kind of chip from a chip positioned in the depressed portion in the step (c), in the depressed portion.